We have three main objectives:
- Apply high-performance computations (HPC) with the quantum-theory-based materials-computation applications developed in the Post-K Project Priority Issue 7 to elucidate and predict the properties of interfaces and thin-film growth surfaces of next-generation energy-saving semiconductor materials and their devices.
- Use the quantum device simulator developed in the Post-K Project Priority Issue 7 to predict the performance of energy-saving power devices, and compare simulation results with experimental data in real devices to propose a novel design of high-performance devices.
- Perform newly developed multi-scale simulations for epitaxial growth of thin films, which are based on the atom-scale reaction mechanism obtained by the quantum-theory-based HPC and on the distributions of temperature and partial pressure in the growth chamber obtained by the fluid simulations, and then contribute to the progress of the fabrication technology of high-quality thin films.
To date, the number of simulator applications that we have developed to achieve the objectives is second-to-none. The main pillar of materials computation applications is the real-space method (code name: RSDFT), which received the 2011 Gordon Bell Prize for Peak-Performance. The RSDFT code is well suited for current as well as future many-core massively parallel architectures such as Fugaku. The RSDFT code continues to evolve as part of the Post-K Project Priority Issue 7, and is expected to realize a 35-times faster performance on Fugaku than the K supercomputer, according to our co-design team. Hence, we will be able to execute quantum materials computations of a surface or interface system consisting of tens of thousands of atoms not as a benchmark but as a production run for the first time in the world. The first-principles molecular dynamics method is also implemented to enhance the application functions, allowing us to perform long-time simulations for unprecedentedly massive systems. Consequently, we can quantum-mechanically determine the surface and interface reaction pathways at a finite temperature and obtain the corresponding reaction free energies. Moreover, this RSDFT and non-equilibrium Green’s function method (code name: NEGF) have been integrated as part of the Post-K Priority Issue project. The integrated method has achieved a level of reproducing the property of the energy-saving wire-type field effect transistor (FET) developed by the Center for Innovative Integrated Electronic Systems of Tohoku University, one of our collaborative partner institutions. You cannot find this level of epitaxial growth simulations based on quantum theory anywhere else in the world. Our simulator applications continue to advance science and technology.
Regarding the experimental activities, we have highly competent experimental groups in representative and collaborative partner institutions responsible for tackling challenges in this project. For instance, the Nagoya University group is developing thin-film growth and device fabrication technologies for nitride semiconductors. The Kyoto University group is developing thin-film growth and device fabrication technologies for SiC semiconductors. The Osaka University group is experimentally investigating power semiconductor device interfaces. The Tohoku University group is developing nanowire MOSFETs. The Fuji Electric group already has a large share in the power semiconductor device market, and the NuFlare Technology group, which is a manufacturer of thin-film growth systems for power semiconductor devices, is a global leader in power electronics. We firmly believe that these close collaborations bring about breakthroughs in power electronics.Data science and computational science have already been combined in two aspects. This project continues this trajectory. One approach is the development of energy functionals that describe the many-electron effect in quantum simulations using deep learning. This approach allows us to conduct real-space simulations of order N (a method whose computational cost is proportional to the target size N), thereby allowing us to target even larger systems. In the other approach, we improve the validity of machine learning by the assimilation of experimental and simulated data in our epitaxial growth simulations (process informatics). We thereby try to clarify the causality relation between atom-scale reactions on the growth surface and in the gas phase, and the temperature distributions and partial pressure of gas sources in the epitaxial growth chamber, aiming to realize a “quantum leap” in the throughput of the formulation of optimum growth conditions.
By the end of the project period, we will complete the following missions:
- Identify defects and impurities at the SiC/SiO2 device interface on the atomscale and elucidate the cause of carrier trapping in metal-oxide-semiconductor field-effect transistors (MOSFETs). In particular, we will elucidate their behavior on various lattice-plane orientations, compare the results from device simulations with experimental data, and optimize device fabrication processes.
- Follow the same steps as 1) at the interfaces of GaN/SiO2, GaN/Al2O3, and GaN/AlSiO devices, and optimize device fabrication processes.
- Elucidate the growth reaction mechanism at the epitaxial GaN growth surface and in the vapor phase, combine the elucidated reaction mechanism and the source-gas fluid simulations to establish a new multiscale simulation technique, and in collaboration with the experimental groups, propose a higher-quality thin-film growth method.
Details of Executed Work
First-Principles Calculations at the Device Interfaces and the Epitaxial Growth Surfaces
1. Clarifications of the Characteristics of Amorphous Gate Insulating Films
A gate insulating film is an essential component for the proper action of semiconductor devices. Mostly, it is made of amorphous materials. Theoretical and computational-science research on the amorphous phase has traditionally been conducted by empirical approaches. Hence, the reliability of the prediction is not assured. In the present research area, we produce real amorphous structures of SiO2 and Al2O3 gate insulating films and their mixed oxides, AlSiO, used in SiC and GaN power devices by melt-quench computations using first-principles molecular dynamics [Car-Parrinello Molecular Dynamics (CPMD) and Born-Oppenheimer Molecular Dynamics (BOMD)] as implemented in the RSDFT. To simulate an amorphous structure, it is necessary to quench as large a system as possible at as slow as possible speed. Considering the performance of RSDFT at Fugaku, we aim to create amorphous structures with a quench speed of 1 degree per picosecond for a system consisting of several thousands of atoms. This feat for such a large-scale disordered system has yet to be accomplished in quantum simulations.
2. Structural Identification of Interfaces of SiC/SiO2, GaN/Gate Insulating Films, and Their Imperfections
Amorphous SiO2 is a suitable gate insulating film for SiC. We determine the structure of the SiC/SiO2 device interface, the atomic-scale structure of various types of defects (defects due to carbon, oxygen, and the stacking of atomic layers, etc.), and the associated formation energies at the interface by the RSDFT calculations. We then find the relative position of the electron energy level caused by the defects in the energy gap of SiC, thereby identifying the carrier trap levels in the devices. We compare the results with the data obtained from the experimental group and provide guidelines for optimizing the device fabrication process to improve MOSFET device characteristics. SiO2, Al2O3, and AlSiO are strong candidates for gate insulating films for GaN power devices. We determine the structures of the interfaces between the amorphous materials created in area 1 above and the crystalline GaN by the RSDFT calculations. We also determine the structures of various types of defects at interfaces, and the associated formation energies at interfaces. We then solve for the relative position of the electron energy level caused by the defects in the energy gap of GaN to compute the carrier trap levels in a device. We also elucidate the atomic-scale structure of the line and planar defects in the GaN epitaxial thin films, and identify point defects and impurities, which may be combined with such line and planar defects. In particular, we clarify the possibility of the formation of a complex consisting of the Mg acceptor and the line defects. . We also investigate the electron energy levels caused by the defects and impurities, and clarify how they are related to carrier transport. Finally, we compare the results with data from the experimental group and provide guidelines for improving the fabrication process to enhance the characteristics of MOSFET devices.
3. Elucidation of Elementary Processes Occurring at GaN and SiC Epitaxial Growth Surfaces
Considering the metalorganic vapor phase epitaxy (MOVPE) of GaN and SiC, we elucidate the elementary processes of reactions on their growth surfaces at atomistic level. We determine the surface step-structure under actual epitaxial growth conditions, and then find the energy barriers along the diffusion pathways of impinging atoms (or molecules) in vicinity of the surface steps by the RSDFT calculations, thus clarifying the diffusion mechanism. This process has been discussed phenomenologically in the framework of step kinetics of the thin-film crystal growth for long time. Our RSDFT large-scale first-principles calculations (of a system consisting of several thousands to tens of thousands of atoms) elucidate the process quantum-mechanically for the first time. We also find energy barriers along the pathways in the incorporation process of impinging atoms at the edge of the step and on the terrace, to completely elucidate the elementary processes of epitaxial growth.
Quantum Simulations of Power Devices and Nanodevices
1. Elucidation of the Characteristics of Power Devices
In this research area, we utilize the knowledge of carrier traps at the interfaces of Si/SiO2, GaN/SiO2, and GaN/AlSiO obtained in the preceding research area, First-Principles Calculations at Device Interfaces and Epitaxial Growth Surfaces, and perform device simulations by introducing trap data to our device simulator. We compare our simulation results with actual measurements, and propose optimum device structures. To improve the power device performance, it is essential to elucidate how carrier traps at the interface affect transistor characteristics such as the transfer characteristic and the IV characteristic. The electronic charge state of the traps in devices varies by the external bias conditions of the devices [Phys. Rev. Lett., 102, 036801 (2009)] and the trapped charge not only acts as a scatterer but also affects screening of other scattering potential [ICSCRM 2019, October 2019]. Therefore, to explore optimized device structures, it is inevitable to perform device simulations by considering spatial and energy distributions of the traps in real device structures, and then to clarify the effects of the traps on the transistor characteristics. First, we use the RSDFT to find the electron state of the two-dimensional inversion layer formed at the MOSFET interface, including carrier-trap states, and determine the energy dispersion of carriers and their scattering probability along the device interface. We then introduce the results into the device simulators, which are based on the non-equilibrium Green’s function (NEGF), Monte Carlo (MC), and quantum drift diffusion (QDD) methods developed in the Post-K Project Priority Issue 7, and perform simulations considering realistic device structures. Finally, we compare the simulation results with data from the experimental group, and propose optimum device structures to improve the power device performance.
2. Creation of a Nanodevice Simulation Environment
In this research area, we use a quantum device simulator based on the non-equilibrium Green’s function (NEGF) method to create a device simulation environment that allows us to accelerate establishing guidelines for the development of nanodevices such as energy-saving nanowire transistors and nanosheet transistors. The Center for Innovative Integrated Electronic Systems (CIES) of Tohoku University has developed a nanowire MOSFET with a 60-nm diameter and a 100-nm gate length. The large-scale quantum device simulator that we have developed in the Post-K Project Priority Issue 7 reproduces the transistor characteristics of this nanowire MOSFET fairly well. At present, however, the simulator does not incorporate scattering processes such as phonon scattering. Consequently, it slightly overestimates the on-state electric current. To compensate for this, we introduce scattering processes into the device simulator, which arise from the interfacial roughness and traps, impurities, or phonons that may affect the variation of the transistor characteristics and device performance in nanodevices. We then compare the simulation results with the transistor characteristics exhibited by real devices and provide bidirectional feedback to improve the simulator. The new simulator, which incorporates scattering processes, will help create an environment that accelerates finding of the nanodevice development guidelines.
Multiscale Epitaxial-Growth Simulations based on Quantum Theory
The breakdown voltage of power devices used in the motor drive system of electric vehicles must exceed 1 kV. To satisfy this condition, the charge carrier density, or equivalently, the number of doped impurities in the unit volume, of the GaN channel layer must be kept below 1.0 x 1016 cm−3 [T. Kachi, Jpn. J. Appl. Phys., 53 (2014) 100210]. In metalorganic vapor phase epitaxy (MOVPE) used for fabricating GaN power devices, trimethylgallium (TMG, Ga(CH3)3) and ammonia (NH3) gas are used as a source of gallium and nitrogen, respectively. Note that ammonia gas contains traces of water (H2O). Due to the chemical composition of these raw materials, the deposited layers are often contaminated with carbon (C) and/or oxygen (O). One way to reduce the concentration of C impurities is to reduce the supply of TMG. However, the reduced TMG supply leads to a decline in the epitaxial growth rate of GaN. Since a faster GaN growth rate (>> 10 µm/h) is required in the industry, a method to either control or eliminate this trade-off is desired. To provide solutions to this problem, we conduct research and development on GaN-MOVPE in the following areas:
1. Elucidation of Vapor-Phase Reaction Processes
The conventional vapor-phase reaction model primarily describes the following two processes: (1) the formation of nitrogen adducts during the reaction and (2) the formation of layers grown by the adsorption of Ga-N molecules in the vapor phase onto the solid-phase surface. However, recent high-resolution time-of-flight mass spectrometry (TOF-MS) by the Nagoya University experimental group revealed that the amount of adduct formation is less than one-thousandth of TMG [K. Nagamatsu et al., Phys. Status Solidi B 254 (2017) 1600737]. Additionally, it was found that the conventional vapor-phase Ga-N formation model cannot account for the dependence of the epitaxial rate on the lattice-plane orientation, indicating an inconsistency in the mentioned vapor-phase reaction model. In this research area, we employ a data assimilation approach evolved in the field of meteorology to build a more precise vapor-phase reaction model based on quantum theory that can reproduce the result of the Nagoya University experimental group.
2. Elucidation of Surface Reaction Processes
Many nitride semiconductor researchers use the correlation diagram of the impurity substitution and defect formation energy and the Fermi level in the bulk state [C. G. van de Walle, J. Appl. Phys. 95 (2004) 3851] to discuss the impurity concentration and the structural stability of defects. However, since impurities are introduced from the epitaxial growth surface, there is a difference between the assumptions made in the diagram and the current debate. In this research area, we make a new correlation diagram of the defect formation energy and the Fermi level by considering the surface states of subsurface layers. The new correlation diagram describing the subsurface layer will replace the conventional correlation diagram describing the bulk state, which we believe will greatly impact research in this field.
3. Correlation Analyses of Surface Energies and Step Densities
The epitaxial growth rate depends on the density of steps and kinks in the epitaxial growth surface. The prediction of the step and kink density entailed the quantum-mechanical analyses of the step-step interaction as well as the interaction between adatoms on the terrace surface and kinks. The K supercomputer can compute the slab model, which consists of several thousands of atoms, but cannot analyze these interactions. In contrast, Fugaku can compute the slab model consisting of tens of thousands of atoms, which allows us to analyze the above interactions. To clarify the correlation among the surface energy, step density, and kink density, we take the analyzed data as input parameters and use them to perform dynamic Monte Carlo simulations.
4. Formulation of Multiscale Physics Model and Verification of the Process Informatics Concept
Combining the results of areas 1, 2, and 3, above, we formulate a multiscale physics model. More specifically, we implement a database of the vapor-phase reactions, surface interactions, and correlation analyses of the surface energy and the step density, which we obtain based on quantum theory, into the fluid analysis software. Our simulation findings will be fed back to the Nagoya University experimental group, which will conduct MOVPE experiments to verify the concept of process informatics in the GaN power device development as a case study.